PIC18F4520 CCP Capture Mode, Read IR signal

PIC18F4520 CCP Capture Mode, Read IR signal
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http://narodstream.ru/pic-urok-12-modul-ccp-rezhim-zaxvata-ik-pult-chast-2/
  1. PIC18F4520
// PIC18F4520 Configuration Bit Settings // 'C' source line config statements // CONFIG1H #pragma config OSC = XT // Oscillator Selection bits (XT oscillator) #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled) #pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled) // CONFIG2L #pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled) #pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled)) #pragma config BORV = 3 // Brown Out Reset Voltage bits (Minimum setting) // CONFIG2H #pragma config WDT = ON // Watchdog Timer Enable bit (WDT enabled) #pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768) // CONFIG3H #pragma config CCP2MX = PORTC // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1) #pragma config PBADEN = ON // PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset) #pragma config LPT1OSC = OFF // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation) #pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled) // CONFIG4L #pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset) #pragma config LVP = ON // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled) #pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode)) // CONFIG5L #pragma config CP0 = OFF // Code Protection bit (Block 0 (000800-001FFFh) not code-protected) #pragma config CP1 = OFF // Code Protection bit (Block 1 (002000-003FFFh) not code-protected) #pragma config CP2 = OFF // Code Protection bit (Block 2 (004000-005FFFh) not code-protected) #pragma config CP3 = OFF // Code Protection bit (Block 3 (006000-007FFFh) not code-protected) // CONFIG5H #pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected) #pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected) // CONFIG6L #pragma config WRT0 = OFF // Write Protection bit (Block 0 (000800-001FFFh) not write-protected) #pragma config WRT1 = OFF // Write Protection bit (Block 1 (002000-003FFFh) not write-protected) #pragma config WRT2 = OFF // Write Protection bit (Block 2 (004000-005FFFh) not write-protected) #pragma config WRT3 = OFF // Write Protection bit (Block 3 (006000-007FFFh) not write-protected) // CONFIG6H #pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected) #pragma config WRTB = OFF // Boot Block Write Protection bit (Boot block (000000-0007FFh) not write-protected) #pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected) // CONFIG7L #pragma config EBTR0 = OFF // Table Read Protection bit (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks) #pragma config EBTR1 = OFF // Table Read Protection bit (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks) #pragma config EBTR2 = OFF // Table Read Protection bit (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks) #pragma config EBTR3 = OFF // Table Read Protection bit (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks) // CONFIG7H #pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) not protected from table reads executed in other blocks) // #pragma config statements should precede project file includes. // Use project enums instead of #define for ON and OFF. #include <xc.h> #define _XTAL_FREQ 4000000 //------------------------------------------------ unsigned char lock=0; unsigned int n=0, i=0; unsigned char rc_code=0, rc_addr=0, rc_code_old=0, rc_addr_old=0; unsigned int result[40]={0}; //------------------------------------------------ void __interrupt(high_priority) ccp(void) { if (PIE1bits.TMR1IE && PIR1bits.TMR1IF) { TMR1=0; // TMR1 Overflow Interrupt Enable bit // 1 = Enables the TMR1 overflow interrupt // 0 = Disables the TMR1 overflow interrupt PIR1bits.TMR1IF = 0; lock=0; n=0; } if(PIR1bits.CCP1IF) { TMR1=0; // CCP1 Interrupt Enable bit // 1 = Enables the CCP1 interrupt // 0 = Disables the CCP1 interrupt PIE1bits.CCP1IE = 0; // CCP1 Interrupt Flag bit // Capture mode: // 1 = A TMR1 register capture occurred (must be cleared in software) // 0 = No TMR1 register capture occurred // Compare mode: // 1 = A TMR1 register compare match occurred (must be cleared in software) // 0 = No TMR1 register compare match occurred // PWM mode: // Unused in this mode. PIR1bits.CCP1IF = 0; if(!lock) { result[n] = CCPR1; n++; if(n>33) { rc_code=0; rc_addr=0; for (i = 0; i < 8; i++) { rc_code >>= 1; rc_addr >>= 1; if(result[i+18]>240) rc_code|=0x80; if(result[i+2]>240) rc_addr|=0x80; } n=0; lock=1; } } PIE1bits.CCP1IE = 1; } } //------------------------------------------------ void main() { TRISB = 0x00; // capture pin TRISC2 = 1; // CCP1 Interrupt Enable bit // 1 = Enables the CCP1 interrupt // 0 = Disables the CCP1 interrupt PIE1bits.CCP1IE = 1; // 0100 = Capture mode, every falling edge CCP1CON = 0X04; // CCP1 Interrupt Flag bit // Capture mode: // 1 = A TMR1 register capture occurred (must be cleared in software) // 0 = No TMR1 register capture occurred // Compare mode: // 1 = A TMR1 register compare match occurred (must be cleared in software) // 0 = No TMR1 register compare match occurred // PWM mode: // Unused in this mode. PIR1bits.CCP1IF = 0; // Timer1 Input Clock Prescale Select bits // 11 = 1:8 Prescale value // 10 = 1:4 Prescale value // 01 = 1:2 Prescale value // 00 = 1:1 Prescale value T1CONbits.T1CKPS0 = 1; T1CONbits.T1CKPS1 = 1; // Timer1 Clock Source Select bit // 1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge) // 0 = Internal clock (FOSC/4) T1CONbits.TMR1CS = 0; // TMR1 Overflow Interrupt Enable bit // 1 = Enables the TMR1 overflow interrupt // 0 = Disables the TMR1 overflow interrupt PIE1bits.TMR1IE = 1; // Global Interrupt Enable bit // When IPEN = 0: // 1 = Enables all unmasked interrupts // 0 = Disables all interrupts INTCONbits.GIE = 1; // Peripheral Interrupt Enable bit // When IPEN = 0: // 1 = Enables all unmasked peripheral interrupts // 0 = Disables all peripheral interrupts INTCONbits.PEIE = 1; // Timer1 On bit // 1 = Enables Timer1 // 0 = Stops Timer1 T1CONbits.TMR1ON = 1; while(1) { __delay_ms(100); if((rc_code!=rc_code_old)||(rc_addr!=rc_addr_old)) { PORTB = rc_code; //sprintf(str1,"Command: 0x%02X ",rc_code); //sprintf(str1,"Addres: 0x%02X ",rc_addr); rc_code_old = rc_code; rc_addr_old = rc_addr; } } } //------------------------------------------------