PIC18F4520 Timer0

PIC18F4520 Timer0
  1. PIC18F4520
// PIC18F4520 Configuration Bit Settings // 'C' source line config statements // CONFIG1H #pragma config OSC = XT // Oscillator Selection bits (XT oscillator) #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled) #pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled) // CONFIG2L #pragma config PWRT = OFF // Power-up Timer Enable bit (PWRT disabled) #pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled)) #pragma config BORV = 3 // Brown Out Reset Voltage bits (Minimum setting) // CONFIG2H #pragma config WDT = ON // Watchdog Timer Enable bit (WDT enabled) #pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768) // CONFIG3H #pragma config CCP2MX = PORTC // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1) #pragma config PBADEN = ON // PORTB A/D Enable bit (PORTB<4:0> pins are configured as analog input channels on Reset) #pragma config LPT1OSC = OFF // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation) #pragma config MCLRE = ON // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled) // CONFIG4L #pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset) #pragma config LVP = ON // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled) #pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode)) // CONFIG5L #pragma config CP0 = OFF // Code Protection bit (Block 0 (000800-001FFFh) not code-protected) #pragma config CP1 = OFF // Code Protection bit (Block 1 (002000-003FFFh) not code-protected) #pragma config CP2 = OFF // Code Protection bit (Block 2 (004000-005FFFh) not code-protected) #pragma config CP3 = OFF // Code Protection bit (Block 3 (006000-007FFFh) not code-protected) // CONFIG5H #pragma config CPB = OFF // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected) #pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected) // CONFIG6L #pragma config WRT0 = OFF // Write Protection bit (Block 0 (000800-001FFFh) not write-protected) #pragma config WRT1 = OFF // Write Protection bit (Block 1 (002000-003FFFh) not write-protected) #pragma config WRT2 = OFF // Write Protection bit (Block 2 (004000-005FFFh) not write-protected) #pragma config WRT3 = OFF // Write Protection bit (Block 3 (006000-007FFFh) not write-protected) // CONFIG6H #pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected) #pragma config WRTB = OFF // Boot Block Write Protection bit (Boot block (000000-0007FFh) not write-protected) #pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected) // CONFIG7L #pragma config EBTR0 = OFF // Table Read Protection bit (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks) #pragma config EBTR1 = OFF // Table Read Protection bit (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks) #pragma config EBTR2 = OFF // Table Read Protection bit (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks) #pragma config EBTR3 = OFF // Table Read Protection bit (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks) // CONFIG7H #pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) not protected from table reads executed in other blocks) // #pragma config statements should precede project file includes. // Use project enums instead of #define for ON and OFF. #include <xc.h> int i=0; void __interrupt(high_priority) myHiIsr(void){ if(INTCONbits.TMR0IF){ i++; INTCONbits.TMR0IF=0; // TMR0 register has overflowed (must be cleared in software) if (i>0) { i = 0; LATBbits.LATB0 = LATBbits.LATB0 == 0 ? 1 : 0; } } } void main(){ TRISBbits.TRISB0 = 0; LATBbits.LATB0 = 0; // datasheet page:92 // Global Interrupt Enable bit // When IPEN = 0: // 1 = Enables all unmasked interrupts // 0 = Disables all interrupts INTCONbits.GIE=1; // TMR0 Overflow Interrupt Enable bit // 1 = Enables the TMR0 overflow interrupt // 0 = Disables the TMR0 overflow interrupt INTCONbits.TMR0IE=1; // TMR0 Overflow Interrupt Flag bit // 1 = TMR0 register has overflowed (must be cleared in software) // 0 = TMR0 register did not overflow INTCONbits.TMR0IF=0; // datasheet page 123, timer0 module // Timer0 On/Off Control bit // 1 = Enables Timer0 // 0 = Stops Timer0 T0CONbits.TMR0ON=1; // Timer0 8-Bit/16-Bit Control bit // 1 = Timer0 is configured as an 8-bit timer/counter // 0 = Timer0 is configured as a 16-bit timer/counter T0CONbits.T08BIT=1; // Timer0 Clock Source Select bit // 1 = Transition on T0CKI pin // 0 = Internal instruction cycle clock (CLKO) T0CONbits.T0CS=0; // Timer0 Source Edge Select bit // 1 = Increment on high-to-low transition on T0CKI pin // 0 = Increment on low-to-high transition on T0CKI pin T0CONbits.T0SE=0; // Timer0 Prescaler Assignment bit // 1 = TImer0 prescaler is not assigned. Timer0 clock input bypasses prescaler. // 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. T0CONbits.PSA=0; // Timer0 Prescaler Select bits // 111 = 1:256 Prescale value // 110 = 1:128 Prescale value // 101 = 1:64 Prescale value // 100 = 1:32 Prescale value // 011 = 1:16 Prescale value // 010 = 1:8 Prescale value // 001 = 1:4 Prescale value // 000 = 1:2 Prescale value T0CONbits.T0PS0=1; T0CONbits.T0PS1=1; T0CONbits.T0PS2=1; while(1); }